1. Field
Exemplary embodiments of the present invention relate to a semiconductor device, and more particularly, to a semiconductor device having a metal gate and a high-k dielectric layer, a complementary metal oxide semiconductor (CMOS) integrated circuit, and a method for fabricating the same.
2. Description of the Related Art
A gate stack structure of a semiconductor device such as a metal oxide semiconductor field-effect transistor (MOSFET) includes a gate dielectric layer formed over a substrate and a gate electrode formed over a gate dielectric layer. In general, silicon oxide (SiO2) has been used for the gate dielectric layer, and silicon has been used for the gate electrode.
When the thickness of the silicon oxide is physically reduced, a control power of a gate voltage may be enhanced to increase a drive current. However, such a physical reduction in the thickness of the gate dielectric layer may degrade an off-state characteristic due to an increase of leakage current caused by direct tunneling.
Meanwhile, in order to implement gate electrodes of an N-channel MOSFET (NMOS) and a P-channel MOSFET (PMOS) during a CMOS integrated circuit process, lithography and ion implantation processes are performed after silicon is deposited. That is, N+-doped silicon which is doped with high-concentration N-type impurities and P+-doped silicon which is doped with high-concentration P-type impurities are formed. As such, the N+-doped silicon is formed to optimize the threshold voltage of the NMOS, and the P+-doped silicon is formed to optimize the threshold voltage of the PMOS. However, the doped silicon has a drive current which is reduced by gate depletion. In particular, boron implanted into the P+-doped silicon of the PMOS may be out-diffused through a subsequent thermal process, and the gate depletion of the PMOS may further increase by 10%, compared with the NMOS. Therefore, the doped silicon may have a limit in optimizing the threshold voltage of each MOS.